A Novel Coating Concept for Electronic and MEMS Packaging

Junghyun Cho, Guangneng Zhang^*, Hyungsuk Lee^*, and Bahgat Sammakia
State University of New York (SUNY), Binghamton, New York 13902-6000

^*Graduate student

ITRS Grand Challenge:

2001-19. Coordinated Design Tools and Simulators to Address Chip, Package and Substrate Codesign

Anticipated Primary Result:

Primary result of this research is the demonstration of the feasibility of using ceramic-organic template-polymer trilayer coatings to be used for harsh environment electronic packages, as well as for MEMS devices. This hybrid coating can also eliminate a hermetic sealing requirement, thereby dramatically reducing manufacturing cost and size.

Background:

Current demands for electronic/MEMS packages include environmental protection from moisture, temperature, and airborne particles. Organic materials (substrates, underfills, etc.) are widely used in packaging applications, but cannot be used under harsh environments. Given that, surface coatings can provide a means of protection. In particular, one of the major bottlenecks for the continued growth of MEMS products has been packaging technology, which is responsible for 75% to 95% of the overall cost of a MEMS device. In addition, many MEMS applications demand inert/vacuum inside the package. Both electronic and MEMS packages must be low cost, miniaturized, and facilitate simple assembly operations. Cost reduction is driving the need to develop a non-hermetic approach according to the International Technology Roadmap for Semiconductors (ITRS). Given the above challenges, we seek to develop a solution precursor processing of strain-tolerant, protective ceramic coating. This coating consists of an integrated inorganic-organic hybrid coating with a hard surface and a thin organic layer. The ceramic coating offers an inert, protective layer, while the organic coating not only acts as a template but also provides strain tolerance for the ceramic coating. With the aid of the encapsulating overmold or coating, the ceramic coating can work as a hermetic packaging alternative.

Description:

This project explores enabling processes that can deposit ceramic coatings on a variety of organic materials used in electronic packages, and silicon structures used in MEMS. The ability to protect base materials from degradation by environmental factors, and to maintain hermeticity is a major goal. For this purpose, we employ a hard surface coating that can act as a multipurpose protective layer. It is natural to choose ceramics as a top coating, since they have a prerequisite hardness and wear/erosion resistance. A major challenge is to avoid the weaknesses that ceramic coatings inherently possess, i.e., low strain tolerance, brittleness and difficulty to produce a uniform, dense layer. In an effort to overcome this difficulty, nanometer scale organic coatings, fabricated by self-assembly processes, are used as a ‘template’ for the subsequent growth of ceramic coatings. This underlying organic coating also acts as a buffer layer by providing compliance for the overlying hard coating upon mechanical and thermomechanical stresses during frequent temperature changes as well as processing. An overarching goal of this project is to have the ability to synthesize and deposit bilayer coatings consisting of top ceramic and underlying organic self-assembled monolayer (SAM) coating on two representative materials; organic materials and silicon. The ceramic coatings will be processed at low temperatures (e.g., < 100°C). We evaluate several oxide materials (e.g., ZrO₂, TiO₂, SiO₂) for the ceramic coatings. Since we are employing a solution precursor technique, we can easily change the composition of the materials, which allows us to test various materials systems. Molecular level understanding of the coating microstructure and micromechanics involved in the coating processes is systematically approached via experimental tools such as AFM and nanoindenter, as well as numerical models. While pursuing our goal, we utilize an integrated design approach to optimize packaging structure so that overall performance (mechanical, thermal, and electrical properties) of the devices is not degraded.

Support for this project is provided by Semiconductor Research Corporation (SRC) & Microelectronics Design Center (MDC).